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gs820e32at-180/166/133/4/5 64k x 32 2mb synchronous burst sram 180 mhz?133 mhz 3.3 v v dd 3.3 v and 2.5 v i/o tqfp commercial temp industrial temp rev: 1.08 1/2009 1/20 ? 2000, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? ft pin for user-configurable flow through or pipelined opera - tion ? dual cycle deselect (dcd) operation ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipelined mode ? byte write ( bw ) and/or global write ( gw ) operation ? common data inputs and data outputs ? clock control, registered, address, data, and control ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec standard 100- lead tqfp package ? rohs-compliant 100-lead tqfp package available functional description applications the gs820e32a is a 2,097,152-bit high performance synchronous sram with a 2- bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enables ( e 1 , e 2 , e 3 ), address burst control inputs ( adsp , adsc , adv ), and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable ( g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used . new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode pin (pin 14 in the tqfp). holding the ft mode pin low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipelined mode, activating the rising-edge-triggered data output register. dcd pipelined reads the gs820e32a is a dcd (dual cycle deselect) pipelined synchronous sram. scd (single cycle deselect) versions are also available. dcd srams pipe line disable commands to the same degree as read commands. dcd srams hold the deselect command for one full cy cle and then begin turning off their outputs just after the second rising edge of the clock. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs820e32a operates on a 3.3 v power supply and all inputs/outputs are 3.3 v- and 2.5 v-compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal circuit. parameter synopsis -180 -166 -133 (-4) -5 pipeline 3-1-1-1 tcycle t kq i dd 5.5 ns 3.2 ns 155 ma 6 ns 3.5 ns 140 ma 7.5 ns 4 ns 115 ma 10 ns 5 ns 90 ma flow through 2-1-1-1 tcycle t kq i dd 9.1 ns 8 ns 100 ma 10 ns 8.5 ns 90 ma 12 ns 10 ns 80 ma 15 ns 12 ns 65 ma
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 2/20 ? 2000, gsi technology gs820e32a 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a nc a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 64k x 32 top view dq b nc dq b dq b dq b dq a dq a dq a dq a nc dq c dq c dq c dq d dq d dq d nc dq c nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 3/20 ? 2000, gsi technology tqfp pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins nc no connect bw i byte write?writes all enabled bytes; active low b a , b b i byte write enable for dq a , dq b data i/os; active low b c , b d i byte write enable for dq c , dq d data i/os; active low ck i clock input signal; active high gw i global write enable?writes all bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advan ce enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 4/20 ? 2000, gsi technology gs820e32a block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0 ? an lbo adv ck adsc adsp gw bw b a b b b c b d e 1 ft g zz power down control memory array 32 32 4 a qd e 2 e 3 dqx1 ? dqx8 1
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 5/20 ? 2000, gsi technology note: there are pull-up devices on the lbo and ft pins and a pull-down device on the zz pin, so t hose input pins can be unconnected and the chip will operate in the default states as specified in the above table. burst counter sequences mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 6/20 ? 2000, gsi technology notes: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. byte write truth table function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 7/20 ? 2000, gsi technology synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low 2. e = t (true) if e 2 = 1 and e 3 = 0; e = f (false) if e 2 = 0 or e 3 = 1 3. w = t (true) and f (false) is defined in the byte write truth table preceding 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 8/20 ? 2000, gsi technology simplified state diagram first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assu mes active use of only the enable (e 1, e 2, e 3 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs, and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs, and assumes adsp is tied high and adv is tied low.
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 9/20 ? 2000, gsi technology simplified state diagram with g first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw notes: 1. the diagram shows supported (tes ted) synchronous state transit ions, plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in gray assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 10/20 ? 2000, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specificati ons quoted are evaluated for worst case at both 2.75 v ? v ddq ? 2.375 v (i.e., 2.5 v i/o) and 3.6 v ? v ddq ? 3.135 v (i.e., 3.3 v i/o) and quoted at whichever condition is worst case. 2. this device features input buffers compat ible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are offer ed in both commercial and industrial temperature ranges. the pa rt number of industrial temperature range versions end with the character ?i?. unless otherwise no ted, all performance specifications quote d are evalu - ated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( ? 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( ? 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended oper ating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v 1 i/o supply voltage v ddq 2.375 2.5 v dd v 1 input high voltage v ih 1.7 ? v dd +0.3 v 2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 0 25 70 ? c 3 ambient temperature (industrial range versions) t a ?40 25 85 ? c 3
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 11/20 ? 2000, gsi technology note: this parameter is sample tested. notes: 1. include scope and jig capacitance. 2. test conditions as specified wi th output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. capacitance (t a = 25 ? c, f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit control input capacitance c i v dd = 3.3 v 3 4 pf input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd +- 2.0 v 50% v dd v il dq vt = 1.25 v 50 ? 30pf * output load 1 * distributed test jig capacitance
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 12/20 ? 2000, gsi technology dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i inzz v dd ? v in ? v ih 0v ?? v in ?? v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i inm v dd ? v in ? v il 0v ?? v in ?? v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?ma, v ddq = 2.375 v 1.7 v output high voltage v oh i oh = ?ma, v ddq = 3.135 v 2.4 v output low voltage v ol i ol = ma 0.4 v operating currents parameter test conditions symbol -180 -166 -133 (-4) -5 unit 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c operating current device selected; all other inputs ? v ih o r ?? v il output open i dd pipeline 155 160 140 145 115 120 90 95 ma i dd flow through 100 105 90 95 80 85 65 70 ma standby current zz ?? v dd ? 0.2 v i sb flow through 10 15 10 15 10 15 10 15 ma deselect current device deselected; all other inputs ?? v ih or ? v il i dd pipeline 35 40 30 35 30 35 25 30 ma i dd flow through 25 30 25 30 20 25 20 25 ma
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 13/20 ? 2000, gsi technology notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above. ac electrical characteristics parameter symbol -180 -166 -133(-4) -5 unit min max min max min max min max pipeline clock cycle time tkc 5.5 ? 6 ? 7.5 ? 10 ? ns clock to output valid tkq ? 3.2 ? 3.5 ? 4 ? 5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 9.1 ? 10 ? 12 ? 15 ? ns clock to output valid tkq ? 8 ? 8.5 ? 10 ? 12 ns clock to output invalid tkqx 3 ? 3 ? 3 ? 3 ? ns clock to output in low-z tlz 1 3 ? 3 ? 3 ? 3 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 4 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 4 ? 5 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 4 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 14/20 ? 2000, gsi technology pipeline mode timing (dcd) begin read a cont deselect deselect write b read c read c+1 read c+2 read c+3 cont deselect deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts tkc tkc tkl tkl tkh tkh q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc hi-z deselected with e1 e2 and e3 only sampled with adsc adsc initiated read ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 15/20 ? 2000, gsi technology flow through mode timing (dcd) begin read a cont deselect write b read c read c+1 read c+2 read c+3 read c deselect thz tkqx tlz th ts tohz toe tkq th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsp and adsc e1 masks adsp adsc initiated read deselected with e1 e1 masks adsp fixed high ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 16/20 ? 2000, gsi technology sleep mode timing application tips single and dual cycle deselect scd devices force the use of ?dummy read cy cles? (read cycles that are launched norm ally, but that are e nded with the output drivers inactive) in a fully synchronous en vironment. dummy read cycles waste perfor mance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple ba nk application (wait states need not be inserted at bank addre ss boundary crossings), but greater care must be exercised to av oid excessive bus contention. tzzr tzzh tzzs hold setup tkl tkl tkh tkh tkc tkc ck adsp adsc zz
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 1/2009 17/20 ? 2000, gsi technology gs820e32a output dri ver characteristics -80 -60 -40 -20 0 20 40 60 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull dow n) v ddq - v out (pull up) i out (ma) 3.6v pd ld 3.3v pd ld 3.1v pd ld 3.1v pu ld 3.3v pu ld 3.6v pu ld pull up driv ers pull down driv ers v ddq vout i out v ss
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice. for latest docum entation see http://www.gsitechnology.com. rev: 1.08 1/2009 18/20 ? 2000, gsi technology tqfp package drawi ng (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y ? notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 ? lead angle 0 ? ? 7 ?
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice. for latest docum entation see http://www.gsitechnology.com. rev: 1.08 1/2009 19/20 ? 2000, gsi technology ordering information for gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 64k x 32 gs820e32at-180 pipeline/flow through tqfp 180/8 c 64k x 32 gs820e32at-166 pipeline/flow through tqfp 166/8.5 c 64k x 32 gs820e32at-133 pipeline/flow through tqfp 133/10 c 64k x 32 gs820e32at-4 pipeline/flow through tqfp 133/10 c 64k x 32 gs820e32at-5 pipeline/flow through tqfp 100/12 c 64k x 32 gs820e32at-180i pipeline/flow through tqfp 180/8 i 64k x 32 gs820e32at-166i pipeline/flow through tqfp 166/8.5 i 64k x 32 gs820e32at-133i pipeline/flow through tqfp 133/10 i 64k x 32 gs820e32at-4i pipeline/flow through tqfp 133/10 i 64k x 32 gs820e32at-5i pipeline/flow through tqfp 100/12 i 64k x 32 gs820e32agt-180 pipeline/flow through rohs-compliant tqfp 180/8 c 64k x 32 gs820e32agt-166 pipeline/flow through rohs-compliant tqfp 166/8.5 c 64k x 32 GS820E32AGT-133 pipeline/flow through rohs-compliant tqfp 133/10 c 64k x 32 gs820e32agt-4 pipeline/flow through rohs-compliant tqfp 133/10 c 64k x 32 gs820e32agt-5 pipeline/flow through rohs-compliant tqfp 100/12 c 64k x 32 gs820e32agt-180i pipeline/flow through rohs-compliant tqfp 180/8 i 64k x 32 gs820e32agt-166i pipeline/flow through rohs-compliant tqfp 166/8.5 i 64k x 32 GS820E32AGT-133i pipeline/flow through rohs-compliant tqfp 133/10 i 64k x 32 gs820e32agt-4i pipeline/flow through rohs-compliant tqfp 133/10 i 64k x 32 gs820e32agt-5i pipeline/flow through rohs-compliant tqfp 100/12 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs820e32at - 166it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow thr ough mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
gs820e32at-180/166/133/4/5 specifications cited are subject to change without notice. for latest docum entation see http://www.gsitechnology.com. rev: 1.08 1/2009 20/20 ? 2000, gsi technology revision history ds/daterev. code: old; new types of changes format or content revisions gs82032 rev 1.03 2/ 2000d;gs820321.04 3/ 2000e content ? first release of a version. added ?a? version to 82032t/q, 820e32tq, and 820h32tq gs820321.04 3/2000e; gs82032a_r1_05 content ? complete rewrite of datasheet in orde r to reflect parts available gs82032a_r1_05; gs82032a_r1_06 content ? reactivated 180 mhz speed bin ? updated format gs82032a_r1_06; gs82032a_r1_07 content ? added pb-free information for tqfp gs82032a_r1_07; gs82032a_r1_08 content ? updated pb-free to rohs-compliant

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